Semiconductor memory devices are important components in presently available industrial and consumer electronics products. For example, computers, mobile phones, and other portable electronics all rely on some form of memory for storing data. While many memory devices are typically available as commodity devices, the need for higher integration has led to the development of embedded memory, which can be integrated with systems, such as microcontrollers and other processing circuits.
Unfortunately, the density of commodity memory cannot match the ever-increasing demand for memory. Hence multiple commodity memories are used together to fulfill the system memory requirements. FIG. 1 shows a known a multi-device memory configuration. Multi-device memory systems can be implemented as a set of silicon chips grouped together in a single package (called a multi chip system—MCP), or a multiplicity of memory device packages grouped together on a printed circuit board.
FIG. 1 is a block diagram of a prior art multi-device system arranged in a multi-drop, or parallel, configuration. Multi-device system 100 includes a memory controller 102 and memory devices 104, 106, 108 and 110. The memory controller 102 is the interface between the memory devices and the system (not shown), while memory devices 104, 106, 108 and 110 can be any type of memory device, or system including embedded memory. While four memory devices are shown, those skilled in the art will understand that multi-device system 100 can include any number of memory devices, but all sharing a common set of read and write data buses. Hence, any one of the memory devices can provide read data through the common set of read databuses, when instructed to through the memory controller 102.
Those skilled in the art understand that multi-device systems, such as the one shown in FIG. 1, is tested at the individual component level and at the system level to ensure robustness of operation. In particular, memory devices are tested at the chip level to ensure that their memory cells are not defective. A defective memory cell is one which does not store data properly, due to fabrication defects or other defects which may occur during fabrication or assembly of the memory device.
One known technique for testing memory devices is the scheme of writing identical test data into two memory banks and then comparing the read out data from a read operation. Those skilled in the art will understand that a memory device can include any number of memory banks, but two are used in the present discussion as examples only. If the memory banks work according to design specifications, the data from one memory bank will match the data from the other memory bank. Otherwise, there is a defective memory cell and the memory device as a whole is considered defective. The conceptual approach of this technique is illustrated in FIG. 2. Test pattern data is first written to two memory banks 202 and 204 of a memory device. This can be done quickly since the same data can be written concurrently into both memory banks 202 and 204. Then the data of both banks 202 and 204 is read out one bit at a time, such that data from bank 202 is compared with data from bank 204 by a logical exclusive OR (XOR) circuit 206. Single bit signal PASS is provided by XOR circuit 206 to indicate the status of the comparison. Differences between the data content of the memory banks will indicate failure of a memory cell. Once identified, defective cells can be replaced with redundant cells using well known redundancy schemes, thereby salvaging an otherwise defective memory device.
Unfortunately, the primary issue with testing is the time required for testing all the memory cells of every memory device of the system. In the previous example, the data of one memory cell of memory bank 202 is compared with the data of one memory cell of memory bank 204. Therefore long testing times will result if all memory devices are tested in sequence, which adds cost to the production cycle of the memory device.
U.S. Pat. No. 5,579,272 to Uchida, entitled “Semiconductor Memory Device with Data Compression test Function and its Testing Method”, addresses the problem of testing time by using data compression. Data compression involves simultaneously testing several memory cells and representing the test result with a number of bits that is smaller than the number of memory cells tested. The most common approach to data compression is to compress multiple bits into a single bit output that indicates a failure when at least one of the input bits indicates a failure. The drawback of this approach is that multiple memory cells are declared faulty in cases where only a single cell is truly defective, although it is possible to mitigate this problem, as illustrated by U.S. Pat. No. 5,913,928 to Morzano, entitled “Data Compression Test Mode Independent of Redundancy.” In Morzano, a failure indication in the compressed test result is followed by individual testing to isolate the defective cells.
Because of the economies that can be achieved by reducing testing time, various efforts have been made to improve upon the circuitry used to compare memory cells and compress the test results. U.S. Pat. No. 5,926,422 to Haukness entitled “Integrated Circuit Memory Device Having Current-Mode Data Compression Test Mode”, U.S. Pat. Nos. 6,295,618 and 6,999,361 to Keeth entitled “Method and Apparatus for Data Compression in Memory Devices”, and U.S. Pat. No. 6,930,936 to Santin entitled “Data Compression Read Mode for Memory Testing” are all examples of patents directed to increasing the speed of the comparison and compression circuitry in a memory device.
Using these well-known techniques, it has been possible to maintain low testing times for individual memory devices in single chip packages despite their increasing size and complexity. It has even been possible to achieve low testing times in multi-device packages arranged in a multi-drop configuration, such as the one illustrated in FIG. 1. The low testing times are still possible in a multi-drop configuration because the memory devices inside the chip can be tested in parallel
The difficulties inherent in testing serially interconnected devices have long been known, as illustrated by U.S. Pat. No. 5,132,635 to Kennedy, entitled “Serial Testing of Removable Circuit Boards on a Backplane Bus”, which illustrates the sequential nature of such testing. The drawback of such sequential testing is that each device is tested in sequence, and therefore a multi-device system containing N chips takes N times as long to test as N single-chip packages or a multi-drop package having the same number of chips.
It is noted that most memory devices should be flexible enough to be used, and tested, in both a multi-drop and serially configured multi-device memory system. As previously discussed, testing of a multi-drop memory system can be done quickly. However, additional dedicated circuits may be required for carrying out multi-device system level testing for serial interconnected configurations. Therefore, the complexity and size of test circuits should be minimized to keep design, fabrication and testing costs minimized.
It is, therefore, desirable to provide a testing scheme for a multi-device memory system arranged in a serial interconnected configuration that can achieve high testing speeds. It is further desirable to minimize the amount of additional test circuits required for implementing the testing scheme.